Atmel AT85DVK-07 Especificaciones descargar pdf (Pagina 96)

AT85C51SND3Bx

7632A–MP3–03/06

Reset Value = 0000 0000b

Table 105. UDPADDH Register

UDPADDH (1.E4h) – USB Dual Port Ram Direct Access High Register

7 6 5 4 3 2 1 0

DPACC - - - - DPADD10:8

Bit

Number

Bit

Mnemonic

Description

7 DPACC

DPRAM Direct Access Bit

Set this bit to directly read the content the Dual-Port RAM (DPR) data through

the UEDATX or UPDATX registers. See

Section “Memory Access Capability” for

more details.

Clear this bit for normal operation and access the DPR through the endpoint

FIFO.

6-3 -

Reserved

The value read from these bits is always 0. Do not set these bits.

2-0 DPADD10:8

DPRAM Address High Bit

DPADD10:8 is the most significant part of DPADD. The least significant part is

provided by the UDPADDL register.

Table 106. UDPADDL Register

UDPADDL (1.E5h) – USB Dual Port Ram Direct Access High Register

7 6 5 4 3 2 1 0

DPADD7:0

Bit

Number

Bit

Mnemonic

Description

7-0 DPADD7:0

DPRAM Address Low Bit

DAPDD7:0 is the least significant part of DPADD. The most significant part is

provided by the UDPADDH register.

Table 107. OTGCON Register

OTGCON (1.E6h) – USB OTG Control Register

7 6 5 4 3 2 1 0

0 - HNPREQ SRPREQ SRPSEL VBUSHWC VBUSREQ VBUSRQC

Bit

Number

Bit

Mnemonic

Description

7 0

OTGCON pagination

This bit must be cleared to access the OTGCON register.

6 -

Reserved

The value read from these bits is always 0. Do not set these bits.

1 2 ... 91 92 93 94 95 96 97 98 99 100 101 ... 262 263

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