Atmel AT85DVK-07 Especificaciones descargar pdf (Pagina 189)

189

AT85C51SND3Bx

7632A–MP3–03/06

Reset Value = 0000 0000b

Table 215. NFIEN Register

NFIEN (1.A6h) – Nand Flash Controller Interrupt Enable Register

7 6 5 4 3 2 1 0

- - - SMCTE ILGLE ECCRDYE ECCERRE STOPE

Bit

Number

Bit

Mnemonic

Description

7-5 -

Reserved

The value read from these bits is always 0. Do not set these bits.

4 SMCTE

SMC Transition Interrupt Enable Bit

Set to enable the SMCTI interrupt.

Clear to disable the SMCTI interrupt.

3 ILGLE

Illegal Operation Interrupt Enable Bit

Set to enable the ILGLI interrupt.

Clear to disable the ILGLI interrupt.

2 ECCRDYE

ECC Ready Interrupt Enable Bit

Set to enable the ECCRDYI interrupt.

Clear to disable the ECCRDYI interrupt.

1 ECCERRE

ECC Error Interrupt Enable Bit

Set to enable the ECCERRI interrupt.

Clear to disable the ECCERRI interrupt.

0 STOPE

Stop Interrupt Enable Bit

Set to enable the STOPI interrupt.

Clear to disable the STOPI interruption.

Table 216. NFUDAT Register

NFUDAT (1.A7h) – Nand Flash Controller User Data Register

7 6 5 4 3 2 1 0

NFUD7 NFUD6 NFUD5 NFUD4 NFUD3 NFUD2 NFUD1 NFUD0

Bit

Number

Bit

Mnemonic

Description

7-0 NFUD7:0

Nand Flash User Data Byte

User defined byte stored in byte position 3 of each spare zone.

1 2 ... 184 185 186 187 188 189 190 191 192 193 194 ... 262 263

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