Atmel AT85DVK-07 Especificaciones descargar pdf (Pagina 187)

187

AT85C51SND3Bx

7632A–MP3–03/06

Reset Value = 0000 0000b

Table 210. NFDAT Register

NFDAT (1.A2h) – Nand-Flash Controller Data Access Register

76543210

DATD7 DATD6 DATD5 DATD4 DATD3 DATD2 DATD1 DATD0

Bit

Number

Bit

Mnemonic Description

7-0 DATD7:0

Data Byte

Writing data sends a data to the currently selected NF.

Reading data gets the data returned by the last read cycle.

Table 211. NFDATF Register

NFDATF (1.A3h) – Nand-Flash Controller Data Access and Fetch Next Data Register

7 6 5 4 3 2 1 0

DATFD7 DATFD6 DATFD5 DATFD4 DATFD3 DATFD2 DATFD1 DATFD0

Bit

Number

Bit

Mnemonic

Description

7-0 DATFD7:0

Data Byte

Writing data sends a data to the currently selected NF.

Reading data gets the data returned by the last read cycle and relaunch a read

cycle on the currently selected NF.

Table 212. NFSTA Register

NFSTA (1.98h) – Nand Flash Controller Status Register

7 6 5 4 3 2 1 0

SMCD SMLCK - NFEOP NECC2 NECC1 NECC0 NFRUN

Bit

Number

Bit

Mnemonic

Description

7 SMCD

SmartMediaCard Detection Flag

Set by hardware when the SMINS input is High.

Cleared by hardware when the SMINS input is Low.

6 SMLCK

SmartMedia Card Lock Flag

Set by hardware when the SMC is write-protected.

Cleared by hardware when the SMC is not write-protected.

5 -

Reserved

The value read from this bit is always 0. Do not set this bit.

4 NFEOP

End Of Page Flag

Set by hardware when the controller stops at the end of the page.

clear by hardware if the controller did not reach the end of the page.

3-1 NECC2:0

Number of ECC Bits

Set/clear by hardware. See Section “ECC Error Management” for more details.

1 2 ... 182 183 184 185 186 187 188 189 190 191 192 ... 262 263

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