Atmel AT85DVK-07 Especificaciones descargar pdf (Pagina 37)

AT85C51SND3Bx

7632A–MP3–03/06

SFR Registers The Special Function Registers (SFRs) of the AT85C51SND3Bx fall into the categories

detailed in

Table 39 to Table 58. Address is identified as “P.XXh” where P can take the

values detailed in Table 38 and XXh is the hexadecimal address from 80h to FFh

Table 38. Page Address Notation

The SFRs mapping within pages is provided together with SFR reset value in Table 58

to Table 58. In these tables, the bit-addressable registers are identified by Note 1.

Note: Available in AT85C51SND3B3 only.

P Comment

Y Register mapped in all pages

3-0 Register mapped in the corresponding page

Table 39. C51 Core SFRs

Mnemonic Add Name 7 6 5 4 3 2 1 0

ACC Y. E0h Accumulator

B Y. F 0h B Register

PSW Y. D 0 h Program Status Word CY AC F0 RS1 RS0 OV F1 P

SP Y.81h Stack Pointer

DPL Y.82h Data Pointer Low Byte

DPH Y.83h Data Pointer High Byte

PPCON Y. C 0 h Peripheral Pagination - - - - PPS3:0

Table 40. Power and System Management

Mnemonic Add Name 7 6 5 4 3 2 1 0

PCON 0.87h Power Control VBCEN VBPEN DCPBST GF0 DCEN* PMLCK PD IDL

PSTA 0.86h Power Status UVDET HVDET - - - WDTRST EXTRST PFDRST

AUXR1 0.A2h Auxiliary Register 1 - - - - GF3 0 - DPS

VBAT 0.85h Battery Voltage Monitoring VBEN VBERR - VB4:0

SVERS 3.97h Silicon Version SV7:0

Table 41. Clock Management Unit SFRs

Mnemonic Add Name 7 6 5 4 3 2 1 0

CKCON 0.8Fh Clock Control - WDX2 - OSCF1:0 T1X2 T0X2 X2

CKEN 0.B9h Clock Enable CKGENE PLLEN - PLOCK MMCKEN - SIOCKEN DFCKEN

CKSEL 0.BAh Clock Selection DNFCKS2:0 PLLCKS1:0 SIOCKS SYSCKS1:0

PLLCLK 0.BCh PLL Clock PLLR3:0 PLLN3:0

MMCCLK 0.BDh MMC Clock MMCCKS2:0 MMCDIV4:0

1 2 ... 32 33 34 35 36 37 38 39 40 41 42 ... 262 263

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