Atmel AT85DVK-07 Especificaciones descargar pdf (Pagina 159)

159

AT85C51SND3Bx

7632A–MP3–03/06

Reset Value = 0000 0000b

2-1 -

Reserved

The value read from these bits is always 0. Do not set these bits.

0 ACCKEN

Audio Controller Clock Enable Bit

Set to enable the Audio Controller Clock.

Clear to disable the Audio Controller Clock.

Table 166. APCON0 Register

APCON0 (1.F2h) – Audio Processor Control Register 0

7 6 5 4 3 2 1 0

0 APCMD6 APCMD5 APCMD4 APCMD3 APCMD2 APCMD1 APCMD0

Bit

Number

Bit

Mnemonic

Description

7 0

Always 0

The value read from this bit is always 0. Can not be set by software.

6-0 APCMD6:0

Audio Processor Operating Command Bits

Codec firmware dependant.

Table 167. APCON1 Register

APCON1 (1.F3h) – Audio Processor Control Register 1

7 6 5 4 3 2 1 0

- - ABACC ABWPR ABRPR ABSPLIT APLOAD DAPEN

Bit

Number

Bit

Mnemonic

Description

7-5 -

Reserved

The value read from these bits is always 0. Do not set these bits.

5 ABACC

Audio Buffer Access Bit

Set to enable buffer access by C51 core.

Clear to enable buffer access by DFC.

4 ABWPR

Audio Buffer Write Pointer Reset Bit

Set to reset the audio buffer write pointer.

Cleared by hardware when write pointer is reset.

Can not be cleared by software.

3 ABRPR

Audio Buffer Read Pointer Reset Bit

Set to reset the audio buffer read pointer.

Cleared by hardware when read pointer is reset.

Can not be cleared by software.

2 ABSPLIT

Audio Buffer Split Bit

Set to configure the audio buffer as a double buffer.

Clear to configure the audio buffer as a single buffer.

Bit

Number

Bit

Mnemonic Description

1 2 ... 154 155 156 157 158 159 160 161 162 163 164 ... 262 263

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