Atmel AT85DVK-07 Especificaciones descargar pdf (Pagina 237)

237

AT85C51SND3Bx

7632A–MP3–03/06

Reset Value= 0000 0000b

3 LCYCT

Cycle Type Selection

Set to select non normalized access cycles (6800 or 8080 interface).

Clear to select normalized access cycles (6800 or 8080 interface).

2 LCEN

LCD Interface Enable

Set to enable the LCD Interface.

Clear to disable the LCD Interface.

1 LCRD

LCD Read Command

Set to initiate a read data or status register from LCD controller.

Cleared by hardware at the end of read.

0 LCRS

LCD Register Select

Set to output high level on LA0/LRS pin during next read or write access.

Clear to output low level on LA0/LRS pin during next read or write access.

This value depends on the LCD controller.

Table 257. LCDSTA Register

LCDSTA (1.8Fh) – LCD Status Register

7 6 5 4 3 2 1 0

- - - - - - - LCBUSY

Bit

Number

Bit

Mnemonic

Description

7:1 -

Reserved

The value read from these bits is always 0. Do not set these bits.

0 LCBUSY

Busy Flag

Set by hardware during any access to the LCD controller and while LCD

controller is busy if busy check process is enabled.

Table 258. LCDBUM Register

LCDBUM (1.8Dh) – LCD Busy Mask Register

7 6 5 4 3 2 1 0

BUM7 BUM6 BUM5 BUM4 BUM3 BUM2 BUM1 BUM0

Bit

Number

Bit

Mnemonic

Description

7:0 BUM7:0

Busy Mask

Set bits to be checked during the busy check process and thus enable the busy

check process.

Clear all bits to disable the busy check process.

Bit

Number

Bit

Mnemonic Description

1 2 ... 232 233 234 235 236 237 238 239 240 241 242 ... 262 263

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