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AT85C51SND3Bx

7632A–MP3–03/06

Watchdog Timer The AT85C51SND3Bx implement a hardware Watchdog Timer (WDT) that automati-

cally resets the chip if it is allowed to time out. The WDT provides a means of recovering

from routines that do not complete successfully due to software or hardware

malfunctions.

Description The WDT consists of a 14-bit prescaler followed by a 7-bit programmable counter. As

shown in

Figure 42, the 14-bit prescaler is fed by the WDT clock detailed in

Section “Clock Controller”.

The Watchdog Timer Reset register (WDTRST, see Table 89) provides control access

to the WDT, while the Watchdog Timer Program register (WDTPRG, see Figure 90) pro-

vides time-out period programming.

Three operations control the WDT:

• Chip reset clears and disables the WDT.

• Programming the time-out value to the WDTPRG register.

• Writing a specific 2-Byte 1Eh-E1h sequence to the WDTRST register clears and

enables the WDT.

Figure 42. WDT Block Diagram

Clock Controller As shown in Figure 43 the WDT clock (F

WDT

) is derived from either the peripheral clock

PER

) or the oscillator clock (F

OSC

) depending on the WTX2 bit in CKCON register.

These clocks are issued from the Clock Controller block as detailed in

Section “Oscillator”, page 27. When WTX2 bit is set, the WDT clock frequency is fixed

and equal to the oscillator clock frequency divided by 2. When cleared, the WDT clock

frequency is equal to the oscillator clock frequency divided by 2 in standard mode or to

the oscillator clock frequency in X2 mode.

Figure 43. WDT Clock Controller and Symbol

WTO2:0

WDTPRG.2:0

WDT

CLOCK

÷ 6

System

1Eh-E1h Decoder

WDTRST

14-bit Prescaler

RST

7-bit Counter

RST

To interna

RST

MATCH

SET

OSC

CLOCK

Pulse Generator

reset

Reset

PER

CLOCK

WDT

CLOCK

OSC

CLOCK

WTX2

CKCON.6

÷ 2

WDT Clock

WDT Clock Symbo

1 2 ... 70 71 72 73 74 75 76 77 78 79 80 ... 262 263

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