Atmel AT85DVK-07 Especificaciones Pagina 68

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68
AT85C51SND3Bx
7632A–MP3–03/06
Figure 36. Timer/Counter x (x = 0 or 1) in Mode 2
Figure 37. Mode 2 Auto-reload Period Formula
Mode 3 (2 x 8-bit Timers) Mode 3 configures Timer 0 such that registers TL0 and TH0 operate as separate 8-bit
Timers (see
Figure 38). This mode is provided for applications requiring an additional 8-
bit Timer or Counter. TL0 uses the Timer 0 control bits C/T0# and GATE0 in TMOD reg-
ister, and TR0 and TF0 in TCON register in the normal manner. TH0 is locked into a
Timer function (counting F
TF1
/6) and takes over use of the Timer 1 interrupt (TF1) and
run control (TR1) bits. Thus, operation of Timer 1 is restricted when Timer 0 is in mode
3.
Figure 39 gives the auto-reload period calculation formulas for both TF0 and TF1
flags.
Figure 38. Timer/Counter 0 in Mode 3: 2 8-bit Counters
Figure 39. Mode 3 Overflow Period Formula
TFx
TCON reg
Overflow
Timer x
Interrup
t
Reques
t
TLx
(8 bits)
THx
(8 bits)
0
1
GATEx
TMOD Reg
C/Tx#
TMOD Reg
INTx
Tx
TIMx
CLOCK
÷ 6
TRx
TCON Reg
TFx
PER
=
F
TIMx
6 (256 – THx)
TF1
TCON.7
TF0
TCON.5
0
1
GATE0
TMOD.3
Overflow
Timer 0
Interrup
t
Reques
t
C/T0#
TMOD.2
INTx
Tx
TIM0
CLOCK
÷ 6
TR0
TCON.4
TL0
(8 bits)
Overflow
Timer 1
Interrup
t
Reques
t
TH0
(8 bits)
TIM0
CLOCK
÷ 6
TR1
TCON.6
TF0
PER
=
F
TIM0
6 (256 – TL0)
TF1
PER
=
F
TIM0
6 (256 – TH0)
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