Atmel AT85DVK-07 Especificaciones descargar pdf (Pagina 188)

188

AT85C51SND3Bx

7632A–MP3–03/06

Reset Value = 0000 0000b

0 NFRUN

Running Flag

Set by hardware to signal that it is currently running.

Cleared by hardware to signal it is not running.

Table 213. NFECC Register

NFECC (1.A4h) – Nand Flash Controller ECC 1 and ECC 2 Register

7 6 5 4 3 2 1 0

NFED7 NFED6 NFED5 NFED4 NFED3 NFED2 NFED1 NFED0

Bit

Number

Bit

Mnemonic

Description

7-0 NFED7:0

Nand Flash ECC 6-byte Data FIFO

Read Mode

Sequential reading returns 2 ECC values of 3 bytes.

Write Mode

Writing any data resets the ECC engine and the FIFO manager.

Table 214. NFINT Register

NFINT (1.A5h) – Nand Flash Controller Interrupt Register

7 6 5 4 3 2 1 0

- - - SMCTI ILGLI ECCRDYI ECCERRI STOPI

Bit

Number

Bit

Mnemonic

Description

7-5 -

Reserved

The value read from these bits is always 0. Do not set these bits.

4 SMCTI

SmartMedia Card Transition Interrupt Flag

Set by hardware every time SMCD bit in NFSTA is toggling.

Shall be cleared by software.

3 ILGLI

ILLEGAL operation Interrupt Flag

Set by hardware when an illegal operation is performed.

Shall be cleared by software.

2 ECCRDYI

ECC Ready Interrupt Flag

Set by hardware when the ECCs (6 bytes) are ready for operation.

This bit is set/clear even if the spare zone is automatically managed (ECCEN).

Shall be cleared by software.

1 ECCERRI

ECC Error Interrupt Flag

Set by hardware when a bad ECC is seen.

Shall be cleared by software.

0 STOPI

Stop Interrupt Flag

Set by hardware when a running (NFRUN= 1) to not running (NFRUN= 0)

transition is met (end of page, end of data transfer, …)

Shall be cleared by software.

Bit

Number

Bit

Mnemonic Description

1 2 ... 183 184 185 186 187 188 189 190 191 192 193 ... 262 263

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