Atmel AT85DVK-07 Especificaciones descargar pdf (Pagina 193)

193

AT85C51SND3Bx

7632A–MP3–03/06

Figure 88. Command Transmission Flow

Command Receiver The end of the response reception is signalled by the EORI flag in MMINT register. This

flag may generate an interrupt request as detailed in

Section “Interrupt”. When this flag

is set, 2 other flags (RXCEN in MMCON1 register and CRC7S in MMSTA register) give

a status on the response received. RXCEN is cleared when the response format is cor

rect or not: the size is the one expected (48 bits or 136 bits) and a valid End bit has been

received, and CRC7S indicates if the CRC7 computation is correct or not. The Flag

CRC7S is cleared when a command is sent to the card and updated when the response

has been received.

Response reading may be aborted by setting and clearing the CRPTR bit in MMCON0

According to the MMC specification delay between a command and a response (for-

mally N

parameter) can not exceed 64 MMC clock periods. To avoid any locking of

the MMC controller when card does not send its response (e.g. physically removed from

the bus), a time-out timer must be launched to recover from such situation. In case of

time-out the command controller and its internal state machine may be reset by setting

and clearing the CCR bit in MMCON2 register.

This time-out may be disarmed when receiving the response.

Command

Transmission

Load Command in

Buffer

MMCMD = index

MMCMD = argument

Configure Response

RXCEN = X

RFMT = X

CRCDIS = X

Transmit Command

TXCEN = 1

1 2 ... 188 189 190 191 192 193 194 195 196 197 198 ... 262 263

Sin comentarios

Atmel AT85DVK-07 Especificaciones Pagina 193