Atmel AT85DVK-07 Especificaciones descargar pdf (Pagina 30)

AT85C51SND3Bx

7632A–MP3–03/06

Figure 19. System Clock Generator Block Diagram and Symbols

Table 26. System Clock Selection

X2 Feature Unlike standard C51 products that require 12 clock periods per machine cycle, the

AT85C51SND3Bx need only 6 clock periods per machine cycle. This feature called the

“X2 feature” can be enabled using the X2 bit

(1)

in CKCON and allows the

AT85C51SND3Bx to operate in 6 or 12 clock periods per machine cycle. As shown in

Figure 19, both CPU and peripheral clocks are affected by this feature. Figure 20 shows

the X2 mode switching waveforms. After reset the standard mode is activated. In stan-

dard mode the CPU and peripheral clock frequency is the oscillator frequency divided by

2 while in X2 mode, it is the oscillator frequency.

Figure 20. Mode Switching Waveforms

DFC/NFC Clock

Generator

In order to optimize the data transfer throughput between the DFC and the NFC, both

peripherals share the same clock frequency. The DFC and NFC clock generator block

diagram is shown in

Figure 21 and is based on a frequency selector.

Frequency selection is done using DNFCKS2:0 bits in CKSEL (see Table 33) according

to Table 27.

Frequency is enabled by setting DNFCKEN bit in CKEN.

SYSCKS1:0 Clock Selection (F

SYS

)

00 F

OSC

(default)

01 24 MHz

10 30 MHz

11 40 MHz

IDL

PCON.0

CKCON.0

SYSCKS1:0

CKSEL.1:0

CLOCK

GEN

24 MHz

30 MHz

40 MHz

SYS

OSC

CLOCK

Peripheral

CPU Core

÷ 2

Clock

PER

CLOCK

Peripheral Clock Symbol

CPU

CLOCK

CPU Core Clock Symbol

AUD

CLOCK

Audio Clock Symbol

Audio Controlle

Clock

SYS

÷ 2

SYS

Clock

X2 bit

X2 ModeSTD Mode STD Mode

1 2 ... 25 26 27 28 29 30 31 32 33 34 35 ... 262 263

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