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AT85C51SND3Bx

7632A–MP3–03/06

Parallel Slave Interface

The AT85C51SND3Bx implement a Parallel Slave Interface (PSI) allowing parallel con-

nection with a host for remote control and data transfer. By using this interface, the

AT85C51SND3Bx can be seen as a multimedia co-processor and be remotely con

trolled by the host.

The main features of the PSI Interface are:

• ARM / I80 glueless interface capability

• 8-bit parallel data bus

• 1-bit address bus

• 16-byte FIFO with MCU interrupt capability

• Bi-directional multimedia bus connection through one DFC Channel

Figure 98 shows a typical PSI host connection. Interface consists in a 8-bit data bus, a

1-bit address bus and read and write signals along with a chip select.

Figure 98. Typical PSI Host Connection

Description The C51 core interfaces with the PSI using the following Special Function Registers:

PSICON (see

Table 231) the control register, PSISTA (see Table 232) the status regis-

ter, PSIDAT (see Table 233) the data register and PSISTH (see Table 234) the host

status register.

The PSI is enabled by setting the PSEN bit in PSICON.

As soon as the PSI is enabled, I/O ports are programmed in input and I/O pull-ups are

disabled.

Figure 99. PSI Block Diagram

SD7:0

AT85C51SND3B

D7:0

HOST

SRD

SWRWR

SA0

SCS

CSx

Px.yINTx

Note: 1. Optional signal for slave to host signaling.

(1)

Control

Manager

SWR

SA0

DFC

Bus

SD7:0

Slave

Decoder

Data

Manager

Interrupt

Controller

CPU

Bus

SRD

SCS

PSI

Interrupt

Request

16-byte FIFO

PER

CLOCK

1 2 ... 202 203 204 205 206 207 208 209 210 211 212 ... 262 263

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