Atmel AT85DVK-07 Especificaciones descargar pdf (Pagina 165)

165

AT85C51SND3Bx

7632A–MP3–03/06

Reset Value = 0000 0000b

Table 180. ACOLG Register (AT85C51SND3B2 and AT85C51SND3B3 only)

ACOLG (2.ECh) – Audio Codec Left Output Gain Register

7 6 5 4 3 2 1 0

- - - AOLG4 AOLG3 AOLG2 AOLG1 AOLG0

Bit

Number

Bit

Mnemonic

Description

7-5 -

Reserved

The value read from these bits is always 0. Do not set these bits.

4-0 AOLG4:0

Audio Output Left Gain

Refer to Table 157 for gain value.

Table 181. ACIPG Register

ACIPG (2.EDh) – Audio Codec Input Preamplifier Gain Register

7 6 5 4 3 2 1 0

- - - - AILPG - AIPG2 AIPG1 AIPG0

Bit

Number

Bit

Mnemonic

Description

7-4 -

Reserved

The value read from these bits is always 0. Do not set these bits.

3 AILPG

AT85C51SND3B2 and AT85C51SND3B3: Audio Input Line Preamplifier Gain

Refer to Table 161 for gain value.

AT85C51SND3B1: Reserved

The value read from this bit is always 0. Do not set this bit.

2-0 AIPG4:0

Audio Input Preamplifier Gain

Refer to Table 160 for gain value.

Table 182. ADICON0 Register

ADICON0 (2.EEh) – Audio DAC Interface Control Register 0

7 6 5 4 3 2 1 0

- - - CSPOL DSIZE OVERS1 OVERS0 ADIEN

Bit

Number

Bit

Mnemonic

Description

7-5 -

Reserved

The value read from these bits is always 0. Do not set these bits.

4 CSPOL

Channel Select DSEL Signal Output Polarity Bit

Set to output the left channel on high level of DSEL output (PCM mode).

Clear to output the left channel on the low level of DSEL output (I

S mode).

3 DSIZE

Audio Data Size Bit

Set to select 32-bit data output format.

Clear to select 16-bit data output format.

1 2 ... 160 161 162 163 164 165 166 167 168 169 170 ... 262 263

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