Atmel AT85DVK-07 Especificaciones descargar pdf (Pagina 82)

AT85C51SND3Bx

7632A–MP3–03/06

Registers

Reset Value = 0000 0000b

Table 94. DFCON Register

DFCON (1.89h) – DFC Control Register

7 6 5 4 3 2 1 0

- DFRES - DFCRCEN DFPRIO1 DFPRIO0 DFABTM DFEN

Bit

Number

Bit

Mnemonic

Description

5 -

Reserved

The value read from this bit is always 0. Do not set this bit.

6 DFRES

Data Flow Controller Reset Bit

Set then clear this bit to reset the Data Flow Controller by software.

5 -

Reserved

The value read from this bit is always 0. Do not set this bit.

4 DFCRCEN

CRC Enable Bit

Set to enable CRC calculation on channel 0.

Clear to disable CRC calculation.

3-2 DFPRIO1:0

Data Flow Channel Priority Assignment Bits

Refer to Table 93 for channel priority assignment description.

1 DFABTM

Data Flow Abort Mode Bit

Set to trigger a delayed abort.

Clear to trigger an immediate abort.

0 DFEN

Data Flow Controller Enable Bit

Set to enable the Data Flow Controller.

Clear to disable the Data Flow Controller.

Table 95. DFCSTA Register

DFCSTA (1.88h Bit Addressable) – DFC Channel Status Register

7 6 5 4 3 2 1 0

DRDY1 SRDY1 EOFI1 DFBSY1 DRDY0 SRDY0 EOFI0 DFBSY0

Bit

Number

Bit

Mnemonic

Description

7 DRDY1

Channel 1 Destination Ready Flag

Set by hardware when the destination peripheral of channel 1 is ready.

Cleared by hardware when the destination peripheral of channel 1 is not ready.

6 SRDY1

Channel 1 Source Ready Flag

Set by hardware when the source peripheral of channel 1 is ready.

Cleared by hardware when the source peripheral of channel 1 is not ready.

5 EOFI1

Channel 1 End Of Data Flow Interrupt Flag

Set by hardware at the end of a channel 1 data flow transfer.

Cleared by software by setting EOFIA1 in DFCCON. Can not be set by software.

4 DFBSY1

Channel 1 Busy Flag

Set by hardware when a transfer is on-going on channel 1.

Cleared by hardware when no transfer is on-going on channel 1.

1 2 ... 77 78 79 80 81 82 83 84 85 86 87 ... 262 263

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