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AT85C51SND3Bx

7632A–MP3–03/06

Special Function Registers

SFR Pagination The AT85C51SND3Bx implement a SFR pagination mechanism which allows mapping

of high number of peripherals in the SFR space. As shown in

Figure 24, four pages are

accessible through the PPCON (Peripheral Pagination Control) register (see Table 37).

The four bits of PPCON: PPS0 to PPS3 are used to select one page as detailed in Table

36. Setting one bit of PPCON using the setb instruction automatically clears the 7 oth-

ers: e.g. if page 0 is selected, selecting page 3 is done by the instruction setb PPS3

which clears PPS0.

By default, after reset selected page is page 0.

The PPCON content is automatically saved in a specific stack at each interrupt service

routine entry during vectorization and restored at exit during

reti execution.

Figure 24. SFR Pagination Block diagram

Table 36. Page Selection Truth Table

Reset Value = 0000 0001b

PPS3 PPS2 PPS1 PPS0 Selected Page

0 0 0 0 Page 0

X X X 1 Page 0

X X 1 0 Page 1

X 1 0 0 Page 2

1 0 0 0 Page 3

Table 37. PPCON Register

PPCON (Y.C0h) – Peripheral Page Control Register

7 6 5 4 3 2 1 0

- - - - PPS3 PPS2 PPS1 PPS0

Bit

Number

Bit

Mnemonic

Description

7-4 -

Reserved

The value read from these bits is always 0. Do not set these bits.

3-0 PPS3:0

Peripheral Page Select Bits

Refer to Table 36 for page decoding information.

SFR DECODER

PPS0

PPCON.0

PPS1

PPCON.1

4 to 2 ENCODER

PPS2

PPCON.2

PPS3

PPCON.3

1 2 ... 31 32 33 34 35 36 37 38 39 40 41 ... 262 263

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