Atmel AT85DVK-07 Especificaciones descargar pdf (Pagina 32)

AT85C51SND3Bx

7632A–MP3–03/06

Table 28. MMC Clock Selection

Table 29. MMC Clock Divider

SIO Clock Generator As detailed in Figure 23, the SIO clock which feeds the internal SIO baud rate generator

can be programmed using SIOCKS bit in CKSEL register according to Table 30 to gen-

erate either the oscillator frequency or a very high frequency allowing very high baud

rate when PLL is enabled. SIO clock is enabled by SIOCKEN bit in CKEN register.

Figure 23. SIO Clock Generator Block Diagram and Symbol

Table 30. SIO Clock Selection

MMCCKS2:0 Clock Selection (F

)

000 F

OSC

(default)

001 60 MHz

010 48 MHz

011 30 MHz

100 24 MHz

101 20 MHz

110 16 MHz

111 F

OSC

÷ 2

MMCDIV4:0 Clock Division

00000 Disabled (no clock out)

≥ 00001 F

MMC

= F

÷ MMCDIV

SIOCKS Clock Selection (F

)

0 F

OSC

1 120 MHz

CLOCK

GEN

120 MHz

SIO

CLOCK

SIO Clock Symbol

SIOCKEN

CKEN.1

SIO Clock

OSC

SIOCKS

CKSEL.2

1 2 ... 27 28 29 30 31 32 33 34 35 36 37 ... 262 263

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