Atmel AT85DVK-07 Especificaciones descargar pdf (Pagina 250)

AT85C51SND3Bx

7632A–MP3–03/06

Table 271. SPI Interface Master AC Timing

= 1.65 to 3.6 V; T

= -40 to +85°C

Note: 1. Value of this parameter depends on software.

Symbol Parameter Min Max Unit

Slave Mode

CHCH

Clock Period 2 T

PER

CHCX

Clock High Time 0.8 T

PER

CLCX

Clock Low Time 0.8 T

PER

SLCH

, T

SLCL

SS Low to Clock edge 100 ns

IVCL

, T

IVCH

Input Data Valid to Clock Edge 40 ns

CLIX

, T

CHIX

Input Data Hold after Clock Edge 40 ns

CLOV,

CHOV

Output Data Valid after Clock Edge 40 ns

CLOX

, T

CHOX

Output Data Hold Time after Clock Edge 0 ns

CLSH

, T

CHSH

SS High after Clock Edge 0 ns

SLOV

SS Low to Output Data Valid 50 ns

SHOX

Output Data Hold after SS High 50 ns

SHSL

SS High to SS Low

(1)

ILIH

Input Rise Time 2 μs

IHIL

Input Fall Time 2 μs

OLOH

Output Rise time 100 ns

OHOL

Output Fall Time 100 ns

Master Mode

CHCH

Clock Period 2 T

PER

CHCX

Clock High Time 0.8 T

PER

CLCX

Clock Low Time 0.8 T

PER

IVCL

, T

IVCH

Input Data Valid to Clock Edge 20 ns

CLIX

, T

CHIX

Input Data Hold after Clock Edge 20 ns

CLOV,

CHOV

Output Data Valid after Clock Edge 40 ns

CLOX

, T

CHOX

Output Data Hold Time after Clock Edge 0 ns

ILIH

Input Data Rise Time 2 μs

IHIL

Input Data Fall Time 2 μs

OLOH

Output Data Rise time 50 ns

OHOL

Output Data Fall Time 50 ns

1 2 ... 245 246 247 248 249 250 251 252 253 254 255 ... 262 263

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