Atmel AT85DVK-07 Especificaciones descargar pdf (Pagina 205)

205

AT85C51SND3Bx

7632A–MP3–03/06

Reset Value = 0000 0000b

Table 226. MMINT Register

MMINT (1.BEh Read Only) – MMC Interrupt Register

7 6 5 4 3 2 1 0

CDETI EORI EOCI EOFI WFRI HFRI EOBI -

Bit

Number

Bit

Mnemonic

Description

7 CDETI

Card Detection Interrupt Flag

Set by hardware every time CDET bit in MMSTA is toggling.

Cleared when reading MMINT.

6 EORI

End of Response Interrupt Flag

Set by hardware at the end of response reception.

Cleared when reading MMINT.

5 EOCI

End of Command Interrupt Flag

Set by hardware at the end of command transmission.

Cleared when reading MMINT.

4 EOFI

End of Frame Interrupt Flag

Set by hardware at the end of frame (stream, single block or multi block) transfer.

Clear when reading MMINT.

3 WFRI

Whole FIFO Ready Interrupt Flag

Set by hardware when 16 bytes can be read in receive mode or written in

transmit mode.

Cleared when reading MMINT.

2 HFRI

Half FIFO Ready Interrupt Flag

Set by hardware when 8 bytes can be read in receive mode or written in transmit

mode.

Cleared when reading MMINT.

1 EOBI

End of Block Interrupt Flag

Set by hardware at the end of block (single block or multi block) transfer.

Cleared when reading MMINT.

0 -

Reserved

The value read from this bit is always 0. Do not set this bit.

Table 227. MMMSK Register

MMMSK (1.BFh) – MMC Interrupt Mask Register

7 6 5 4 3 2 1 0

MCBM EORM EOCM EOFM WFRM HFRM EOBM -

Bit

Number

Bit

Mnemonic

Description

7 CDETM

Card Detection Interrupt Mask Bit

Set to prevent CDETI flag from generating an interrupt.

Clear to allow CDETI flag to generate an interrupt.

1 2 ... 200 201 202 203 204 205 206 207 208 209 210 ... 262 263

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