Atmel AT85DVK-07 Especificaciones descargar pdf (Pagina 35)

AT85C51SND3Bx

7632A–MP3–03/06

Reset Value = 0000 0000b

Table 33. CKSEL Register

CKSEL (0.BAh) – Clock Selection Register

7 6 5 4 3 2 1 0

DNFCKS2 DNFCKS1 DFCCKS0 PLLCKS1 PLLCKS0 SIOCKS SYSCKS1 SYSCKS0

Bit

Number

Bit

Mnemonic

Description

7-5 DNFCKS2:0

DFC/NFC Clock Select Bits

Refer to Table 27 for information on selected clock value.

4-3 PLLCKS1:0

PLL Reverse Clock Select Bits

Refer to Table 24 for information on selected clock value.

2 SIOCKS

SIO Clock Select Bit

Refer to Table 30 for information on divided clock value.

1-0 SYSCKS1:0

System Clock Select Bits

Refer to Table 26 for information on divided clock value.

Table 34. PLLCLK Register

PLLCLK (0.BCh) – PLL Clock Control Register

7 6 5 4 3 2 1 0

PLLR3 PLLR2 PLLR1 PLLR0 PLLN3 PLLN2 PLLN1 PLLN0

Bit

Number

Bit

Mnemonic

Description

7-4 PLLR3:0

PLL R Divider Bits

4-bit R divider, R from 1 (PLLR3:0 = 0000) to 16 (PLLR3:0 = 1111).

3-0 PLLN3:0

PLL N Divider Bits

4-bit N divider, N from 1 (PLLN3:0 = 0000) to 16 (PLLN3:0 = 1111).

Table 35. MMCCLK Register

MMCCLK (0.BDh) – MMC Clock Control Register

7 6 5 4 3 2 1 0

MMCCKS2 MMCCKS1 MMCCKS0 MMCDIV4 MMCDIV3 MMCDIV2 MMCDIV1 MMCDIV0

Bit

Number

Bit

Mnemonic

Description

7-5 MMCCKS2:0

MMC Clock Select Bits

Refer to Table 28 for information on selected clock value.

4-0 MMCDIV4:0

MMC Clock Divider Bits

Refer to Table 29 for information on divided clock value.

1 2 ... 30 31 32 33 34 35 36 37 38 39 40 ... 262 263

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