Atmel AT85DVK-07 Especificaciones descargar pdf (Pagina 132)

132

AT85C51SND3Bx

7632A–MP3–03/06

“Manual” Mode The TXOUT bit is set by hardware when the current bank becomes free. This triggers an

interrupt if the TXOUTE bit is set. The FIFOCON bit is set at the same time. The CPU

writes into the FIFO and clears the FIFOCON bit to allow the USB controller to send the

data. If the OUT Pipe is composed of multiple banks, this also switches to the next data

bank. The TXOUT and FIFOCON bits are automatically updated by hardware regarding

the status of the next bank.

OUT

DATA

(bank 0)

ACK

TXOUT

FIFOCON

Example with 1 OUT data bank

write data from CPU

BANK 0

Example with 2 OUT data banks

SW SW

OUT

DATA

(bank 0)

ACK

TXOUT

FIFOCON

write data from CPU

BANK 0

SW SW

OUT

DATA

(bank 1)

ACK

write data from CPU

BANK 0

write data from CPU

BANK 1

write data from CPU

BANK0

Example with 2 OUT data banks

OUT

DATA

(bank 0)

ACK

TXOUT

FIFOCON

write data from CPU

BANK 0

SW SW

write data from CPU

BANK 1

write data from CPU

BANK0

OUT

DATA

(bank 1)

ACK

1 2 ... 127 128 129 130 131 132 133 134 135 136 137 ... 262 263

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