Atmel AT85DVK-07 Especificaciones descargar pdf (Pagina 123)

123

AT85C51SND3Bx

7632A–MP3–03/06

Table 126. UEINTX Register (bit addressable)

UEINTX (1.C8h) – USB Endpoint Interrupt Register

7 6 5 4 3 2 1 0

FIFOCON NAKINI RWAL NAKOUTI RXSTPI RXOUTI STALLI TXINI

Bit

Number

Bit

Mnemonic

Description

7 FIFOCON

FIFO Control Bit

For OUT and SETUP Endpoint:

Set by hardware when a new OUT message is stored in the current bank, at the

same time than RXOUT or RXSTP.

Clear to free the current bank and to switch to the following bank. Setting by

software has no effect.

For IN Endpoint:

Set by hardware when the current bank is free, at the same time than TXIN.

Clear to send the FIFO data and to switch the bank. Setting by software has no

effect.

6 NAKINI

NAK IN Received Interrupt Flag

Set by hardware when a NAK handshake has been sent in response of a IN

request from the host. This triggers an USB interrupt if NAKINE is sent.

Shall be cleared by software. Setting by software has no effect.

5 RWAL

Read/Write Allowed Flag

Set by hardware to signal:

- for an IN endpoint: the current bank is not full i.e. the firmware can push data

into the FIFO,

- for an OUT endpoint: the current bank is not empty, i.e. the firmware can read

data from the FIFO.

The bit is never set if STALLRQ is set, or in case of error.

Cleared by hardware otherwise.

This bit shall not be used for the control endpoint.

4 NAKOUTI

NAK OUT Received Interrupt Flag

Set by hardware when a NAK handshake has been sent in response of a

OUT/PING request from the host. This triggers an USB interrupt if NAKOUTE is

sent.

Shall be cleared by software. Setting by software has no effect.

3 RXSTPI

Received SETUP Interrupt Flag

Set by hardware to signal that the current bank contains a new valid SETUP

packet. An interrupt (EPINTx) is triggered (if enabled).

Shall be cleared by software to handshake the interrupt. Setting by software has

no effect.

This bit is inactive (cleared) if the endpoint is an IN endpoint.

RXOUTI /

KILLBK

Received OUT Data Interrupt Flag

Set by hardware to signal that the current bank contains a new packet. An

interrupt (EPINTx) is triggered (if enabled).

Shall be cleared by software to handshake the interrupt. Setting by software has

no effect.

Kill Bank IN Bit

Set this bit to kill the last written bank.

Cleared by hardware when the bank is killed. Clearing by software has no effect.

See Section “Abort” for more details on the Abort.

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