145
AT85C51SND3Bx
7632A–MP3–03/06
Table 148. UPINTX Register
UPINTX (1.C8h) – USB Pipe Interrupt Register
7 6 5 4 3 2 1 0
FIFOCON NAKEDI RWAL PERRI TXSTPI TXOUTI RXSTALLI RXINI
Bit
Number
Bit
Mnemonic
Description
7 FIFOCON
FIFO Control
For OUT and SETUP Pipe:
Set by hardware when the current bank is free, at the same time than TXOUT or
TXSTP.
Clear to send the FIFO data and to switch the bank. Setting by software has no
effect.
For IN Pipe:
Set by hardware when a new IN message is stored in the current bank, at the
same time than RXIN.
Clear to free the current bank and to switch to the following bank. Setting by
software has no effect.
6 NAKEDI
NAK Handshake received
Set by hardware when a NAK has been received on the current bank of the Pipe.
This triggers an interrupt if the NAKEDE bit is set in the UPIENX register.
Shall be clear to handshake the interrupt. Setting by software has no effect.
5 RWAL
Read/Write Allowed
OUT Pipe:
Set by hardware when the firmware can write a new data into the Pipe FIFO.
Cleared by hardware when the current Pipe FIFO is full.
IN Pipe:
Set by hardware when the firmware can read a new data into the Pipe FIFO.
Cleared by hardware when the current Pipe FIFO is empty.
This bit is also cleared by hardware when the RXSTALL or the PERR bit is set
4 PERRI
PIPE Error
Set by hardware when an error occurs on the current bank of the Pipe. This
triggers an interrupt if the PERRE bit is set in the UPIENX register. Refers to the
UPERRX register to determine the source of the error.
Automatically cleared by hardware when the error source bit is cleared.
3 TXSTPI
SETUP Bank ready
Set by hardware when the current SETUP bank is free and can be filled. This
triggers an interrupt if the TXSTPE bit is set in the UPIENX register.
Shall be cleared to handshake the interrupt. Setting by software has no effect.
2 TXOUTI
OUT Bank ready
Set by hardware when the current OUT bank is free and can be filled. This
triggers an interrupt if the TXOUTE bit is set in the UPIENX register.
Shall be cleared to handshake the interrupt. Setting by software has no effect.
1
RXSTALLI /
CRCERR
STALL Received / Isochronous CRC Error
Set by hardware when a STALL handshake has been received on the current
bank of the Pipe. The Pipe is automatically frozen. This triggers an interrupt if the
RXSTALLE bit is set in the UPIENX register.
Shall be cleared to handshake the interrupt. Setting by software has no effect.
For Isochronous Pipe:
Set by hardware when a CRC error occurs on the current bank of the Pipe. This
triggers an interrupt if the TXSTPE bit is set in the UPIENX register.
Shall be cleared to handshake the interrupt. Setting by software has no effect.
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