Atmel AT85DVK-07 Especificaciones descargar pdf (Pagina 204)

204

AT85C51SND3Bx

7632A–MP3–03/06

Reset Value = 0000 0000b

Reset Value = XX00 0000b, depends wether a card is present in the socket or not and if

it is locked or not.

Bit

Number

Bit

Mnemonic

Description

7-0 BLEN7:0

Block Length LSB

Refer to Ta bl e 220 for byte description

Table 225. MMSTA Register

MMSTA (1.B5h Read Only) – MMC Status Register

7 6 5 4 3 2 1 0

SDWP CDET CBUSY CRC16S DATFS CRC7S WFRS HFRS

Bit

Number

Bit

Mnemonic

Description

7 SDWP

SD Card Write Protect Bit

Set by hardware when the SD card socket WP switch is opened.

Cleared by hardware when the SD card socket WP switch is closed.

6 CDET

Card Detection Bit

Set by hardware when the SD card socket presence switch is opened.

Cleared by hardware when the SD card socket presence switch is closed.

5 CBUSY

Card Busy Flag

Set by hardware when the card sends a busy state on the data line.

Cleared by hardware when the card no more sends a busy state on the data line.

4 CRC16S

CRC16 Status Bit

Transmission mode

Set by hardware when the token response reports a bad CRC.

Cleared by software by setting DCR bit in MMCON2.

Reception mode

Set by hardware when the CRC16 received in the data block is not correct.

Cleared by software by setting DCR bit in MMCON2.

3 DATFS

Data Format Status Bit

Transmission mode

Set by hardware when the format of the token response is correct.

Cleared by hardware when the format of the token response is not correct.

Reception mode

Set by hardware when the format of the frame is correct.

Cleared by hardware when the format of the frame is not correct.

2 CRC7S

CRC7 Status Bit

Set by hardware when the CRC7 computed in the response is correct.

Cleared by hardware when the CRC7 computed in the response is not correct.

This bit is not relevant when CRCDIS is set.

1 WFRS

Whole FIFO Ready Status Bit

Set by hardware when 16 bytes can be read in receive mode or written in

transmit mode.

Cleared by hardware when FIFO is not ready.

0 HFRS

Half FIFO Ready Status Bit

Set by hardware when 8 bytes can be read in receive mode or written in transmit

mode.

Cleared by hardware when FIFO is not ready.

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