Atmel AT85DVK-07 Especificaciones descargar pdf (Pagina 201)

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AT85C51SND3Bx

7632A–MP3–03/06

Figure 96. SD Card Write Protection Input Block Diagram

Interrupt As shown in Figure 97, the MMC controller implements eight interrupt sources reported

in CDETI, EORI, EOCI, EOFI, WFRI, HFRI and EOBI flags in MMCINT register. These

flags are detailed in the previous sections.

All these sources are maskable separately using CDETM, EORM, EOCM, EOFM,

WFRM, HFRM and EOBM mask bits respectively in MMMSK register.

The interrupt request is generated each time an unmasked flag is set, and the global

MMC controller interrupt enable bit is set (EMMC in IEN1 register).

Reading the MMINT register automatically clears the interrupt flags (acknowledgment).

This implies that register content must be saved, and tested flag by flag to be sure not to

forget any interrupts.

Figure 97. MMC Controller Interrupt System

SDWP

MMSTA.7

SDLCK

IOVDD

HFRM

MMMSK.2

EOFM

MMMSK.4

EORM

MMMSK.6

MMC

Interrup

CDETI

MMINT.7

EOCM

MMMSK.5

EMMC

IEN1.5

CDETM

MMMSK.7

EOFI

MMINT.4

WFRM

MMMSK.3

EORI

MMINT.6

WFRI

MMINT.3

EOCI

MMINT.5

EOBM

MMMSK.1

HFRI

MMINT.2

EOBI

MMINT.1

Reques

1 2 ... 196 197 198 199 200 201 202 203 204 205 206 ... 262 263

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