Atmel AT85DVK-07 Especificaciones descargar pdf (Pagina 59)

AT85C51SND3Bx

7632A–MP3–03/06

Registers

Reset Value = 0000 0000b

Table 72. IEN0 Register

IEN0 (0.A8h) – Interrupt Enable Register 0

7 6 5 4 3 2 1 0

EA EAUP EDFC ES ET1 EX1 ET0 EX0

Bit

Number

Bit

Mnemonic

Description

7 EA

Enable All Interrupt Bit

Set to enable all interrupts.

Clear to disable all interrupts.

If EA = 1, each interrupt source is individually enabled or disabled by setting or

clearing its interrupt enable bit.

6 EAUP

AUP Interrupt Enable Bit

Set to enable audio processor interrupt.

Clear to disable audio processor interrupt.

5 EDFC

DFC Enable Bit

Set to enable data flow interrupt.

Clear to disable data flow interrupt.

4 ES

SIO Interrupt Enable Bit

Set to enable serial port interrupt.

Clear to disable serial port interrupt.

3 ET1

T1 Overflow Interrupt Enable Bit

Set to enable timer 1 overflow interrupt.

Clear to disable timer 1 overflow interrupt.

2 EX1

EX1 Interrupt Enable bit

Set to enable external interrupt 1.

Clear to disable external interrupt 1.

1 ET0

T0 Overflow Interrupt Enable Bit

Set to enable timer 0 overflow interrupt.

Clear to disable timer 0 overflow interrupt.

0 EX0

EX0 Interrupt Enable Bit

Set to enable external interrupt 0.

Clear to disable external interrupt 0.

1 2 ... 54 55 56 57 58 59 60 61 62 63 64 ... 262 263

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