Atmel AT85DVK-07 Especificaciones descargar pdf (Pagina 146)

146

AT85C51SND3Bx

7632A–MP3–03/06

Reset Value = 0000 0000b

0 RXINI

IN Data received

Set by hardware when a new USB message is stored in the current bank of the

Pipe. This triggers an interrupt if the RXINE bit is set in the UPIENX register.

Shall be cleared to handshake the interrupt. Setting by software has no effect.

Table 149. UPIENX Register

UPIENX (1.D2h) – USB Pipe Interrupt Enable Register

7 6 5 4 3 2 1 0

FLERRE NAKEDE - PERRE TXSTPE TXOUTE RXSTALLE RXINE

Bit

Number

Bit

Mnemonic

Description

7 FLERRE

Flow Error Interrupt enable

Set to enable the OVERFI and UNDERFI interrupts.

Clear to disable the OVERFI and UNDERFI interrupts.

6 NAKEDE

NAK Handshake Received Interrupt Enable

Set to enable the NAKEDI interrupt.

Clear to disable the NAKEDI interrupt.

5 -

Reserved

The value read from this bit is always 0. Do not set this bit.

4 PERRE

PIPE Error Interrupt Enable

Set to enable the PERRI interrupt.

Clear to disable the PERRI interrupt.

3 TXSTPE

SETUP Bank ready Interrupt Enable

Set to enable the TXSTPI interrupt.

Clear to disable the TXSTPI interrupt.

2 TXOUTE

OUT Bank ready Interrupt Enable

Set to enable the TXOUTI interrupt.

Clear to disable the TXOUTI interrupt.

1 RXSTALLE

STALL Received Interrupt Enable

Set to enable the RXSTALLI interrupt.

Clear to disable the RXSTALLI interrupt.

0 RXINE

IN Data received Interrupt Enable

Set to enable the RXINI interrupt.

Clear to disable the RXINI interrupt.

Table 150. UPDATX Register

UPDATX (1.D3h) – USB Pipe Data Register

7 6 5 4 3 2 1 0

PDAT7 PDAT6 PDAT5 PDAT4 PDAT3 PDAT2 PDAT1 PDAT0

Bit

Number

Bit

Mnemonic Description

1 2 ... 141 142 143 144 145 146 147 148 149 150 151 ... 262 263

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