Atmel AT85DVK-07 Especificaciones descargar pdf (Pagina 220)

220

AT85C51SND3Bx

7632A–MP3–03/06

Reset Value = 0000 0000b

Table 243. SFCON Register

SFCON (0.95h) – SIO Flow Control Register

7 6 5 4 3 2 1 0

OVRSF3 OVRSF2 OVRSF1 OVRSF0 CTSEN RTSEN RTSTH1 RTSTH0

Bit

Number

Bit

Mnemonic

Description

7-4 OVRSF3:0

Over Sampling Factor Bits

Number of time a data bit is sampled for level determination.

Oversampling factor = OVRSF3:0 + 1.

3 CTSEN

Clear To send Enable Bit

Set to enable transmission hardware flow control using CTS signal.

Clear to disable transmission hardware flow control.

2 RTSEN

Request To send Enable Bit

Set to enable reception hardware flow control using RTS signal.

Clear to disable reception hardware flow control.

1-0 RTSTH1:0

Request To send Assertion Threshold

Refer to Table 241 for information on threshold values.

Table 244. SINT Register

SINT (1.A8h) – SIO Interrupt Source Register

7 6 5 4 3 2 1 0

- - EOTI OEI PEI FEI TI RI

Bit

Number

Bit

Mnemonic

Description

7 -

Reserved

The value read from this bit is always 0. Do not set this bit.

6 -

Reserved

The value read from this bit is indeterminate. Do not set this bit.

5 EOTI

End Of Transmission Interrupt Flag

Set by hardware when both Tx FIFO and Tx shift register are empty: actual end

of transmission.

Cleared by hardware when the Tx FIFO or Tx shift register are not empty.

4 OEI

Overrun Reception Error Interrupt Flag

Set by hardware when a character is received while the Rx shift register is full

(Rx FIFO full).

Clear by software to acknowledge interrupt.

3 PEI

Parity Reception Error Interrupt Flag

Set by hardware when a parity error occurs in a received character.

Clear by software to acknowledge interrupt.

2 FEI

Framing Reception Error Interrupt Flag

Set by hardware when a framing error occurs in a received character.

Clear by software to acknowledge interrupt.

1 2 ... 215 216 217 218 219 220 221 222 223 224 225 ... 262 263

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