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AT85C51SND3Bx

7632A–MP3–03/06

Figure 94. Data Block Reception Flows

Card Management

Card Detect Input As shown in Figure 95 the SDINS (MMC/SD Card Detect) input implements an internal

pull-up, in order to provide static high level when card is not present in the socket.

SDINS level is reported by CDET bit

(1)

in MMSTA.

As soon as MMC controller is enabled, all level modifications on SDINS input from H to

L or from L to H (card insertion or removal) set CDETI, the Card Detect Interrupt flag in

MMINT (see

Table 226).

Note: 1. CDET bit is not relevant until MMC controller is enabled (MMCEN = 1).

Figure 95. Card Detection Input Block Diagram

Card Lock Input As shown in Figure 96 the SDLCK (SD Lock) input implements an internal pull-up, in

order to provide static high level when card is not present in the socket.

SDLCK level is reported by SDWP bit

(1)

in MMSTA register.

Note: 1. SDWP bit is not relevant until MMC controller is enabled (MMCEN = 1) and a card is

present in the socket (CDET = 0).

Data Block

Reception

Start Transmission

DATEN = 1

FIFO Full?

HFRS = 1?

FIFO Reading

read 8 data from MMDAT

No More Data

To Receive?

a. Polling mode

Data Block

Initialization

Start Reception

DATEN = 1

Data Block

Reception ISR

FIFO Reading

read 8 data from MMDAT

No More Data

To Receive?

b. Interrupt mode

FIFO Full?

HFRI = 1?

Mask FIFO Full

HFRM = 1

Unmask FIFO Full

HFRM = 0

CDETI

MMINT.7

SDINS

IOVDD

CDET

MMSTA.6

1 2 ... 195 196 197 198 199 200 201 202 203 204 205 ... 262 263

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