Atmel AT85DVK-07 Especificaciones descargar pdf (Pagina 67)

AT85C51SND3Bx

7632A–MP3–03/06

Figure 32. Timer/Counter x (x = 0 or 1) in Mode 0

Figure 33. Mode 0 Overflow Period Formula

Mode 1 (16-bit Timer) Mode 1 configures Timer 0 as a 16-bit Timer with TH0 and TL0 registers connected in

cascade (see

Figure 34). The selected input increments TL0 register. Figure 35 gives

the overflow period calculation formula when in timer mode.

Figure 34. Timer/Counter x (x = 0 or 1) in Mode 1

Figure 35. Mode 1 Overflow Period Formula

Mode 2 (8-bit Timer with Auto-

Reload)

Mode 2 configures Timer 0 as an 8-bit Timer (TL0 register) that automatically reloads

from TH0 register (see

Figure 36). TL0 overflow sets TF0 flag in TCON register and

reloads TL0 with the contents of TH0, which is preset by software. When the interrupt

request is serviced, hardware clears TF0. The reload leaves TH0 unchanged. The next

reload value may be changed at any time by writing it to TH0 register.

Figure 37 gives

the auto-reload period calculation formula when in timer mode.

TFx

TCON Reg

GATEx

TMOD Reg

Overflow

Timer x

Interrup

Reques

C/Tx#

TMOD Reg

THx

(8 bits)

INTx

TIMx

CLOCK

÷ 6

TRx

TCON Reg

TLx

(5 bits)

6 ⋅ (16384 – (THx, TLx))

TFx

PER

TIMx

TFx

TCON Reg

GATEx

TMOD Reg

Overflow

Timer x

Interrup

Reques

C/Tx#

TMOD Reg

THx

(8 bits)

INTx

TIMx

CLOCK

÷ 6

TRx

TCON Reg

TLx

(8 bits)

6 ⋅ (65536 – (THx, TLx))

TFx

PER

TIMx

1 2 ... 62 63 64 65 66 67 68 69 70 71 72 ... 262 263

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