Atmel AT85DVK-07 Especificaciones Pagina 203

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AT85C51SND3Bx
7632A–MP3–03/06
Reset Value = 0000 0000b
Reset Value = 0000 0000b
2 DATEN
Data Transfer Enable Bit
Set to enable data transmission or reception immediately or after response has
been received.
Cleared by hardware after the CRC reception in reception mode or after the busy
status if any in transmission mode.
1 RXCEN
Response Command Enable Bit
Set to enable the reception of a response following a command transmission.
Cleared by hardware when response is received.
0 TXCEN
Command Transmission Enable Bit
Set to enable transmission of the command FIFO to the card.
Cleared by hardware when command is transmitted.
Table 223. MMCON2 Register
MMCON2 (1.B3h) – MMC Control Register 2
7 6 5 4 3 2 1 0
FCK DCR CCR DBSIZE1 DBSIZE0 DATD1 DATD0 MMCEN
Bit
Number
Bit
Mnemonic
Description
7 FCK
MMC Force Clock Bit
Set to enable the MCLK clock out permanently.
Clear to disable the MCLK clock and enable flow control.
6 DCR
Data Controller Reset Bit
Set to reset the data line controller in case of transfer abort, or to reset CRC16S
bit after an error occurs.
Cleared by hardware after the data line controller reset is achieved.
5 CCR
Command Controller Reset Bit
Set to reset the command line controller in case of transfer abort.
Cleared by hardware after the data line controller reset is achieved.
4-3 DBSIZE1:0
Data Bus Size
Refer to Ta bl e 219 for bits description.
2-1 DATD1:0
Data Transmission Delay Bits
Used to delay the data transmission after a response from 3 MMC clock periods
(all bits cleared) to 9 MMC clock periods (all bits set) by step of 2 MMC clock
periods.
0 MMCEN
MMC Clock Enable Bit
Set to enable the MMC clocks and activate the MMC controller.
Clear to disable the MMC clocks and freeze the MMC controller.
Table 224. MMBLP Register
MMCON2 (1.B4h) – MMC Block Length LSB Register
7 6 5 4 3 2 1 0
BLEN7 BLEN6 BLEN5 BLEN4 BLEN3 BLEN2 BLEN1 BLEN0
Bit
Number
Bit
Mnemonic Description
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