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AT85C51SND3Bx

7632A–MP3–03/06

Memory Space The AT85C51SND3Bx provide an “all in one” 64K bytes of RAM split between the three

standard C51 memory segments:

•CODE

•DATA

•XDATA

To satisfy application needs in term of CODE and XDATA sizes, size and base address

of XDATA and CODE segments and base address of DATA segment can be dynami

cally configured.

Figure 25 shows the memory space organization.

Figure 25. Memory Organization

Memory Segments

CODE Segment The AT85C51SND3Bx execute up to 64K Bytes of program/code memory.

The AT85C51SND3Bx implement an additional 4K Bytes of on-chip boot ROM memory.

This boot memory is delivered programmed with a boot strap software allowing loading

of the application code from the Nand Flash Memory to the internal RAM. It also con

tains a boot loader software allowing In-System Programming (ISP).

DATA Segment The DATA segment is mapped in two separate segments:

– The lower 128 Bytes RAM segment

– The upper 128 Bytes RAM segment

Lower 128 Bytes The lower 128 Bytes of RAM (see Figure 26) are accessible from address 00h to 7Fh

using direct or indirect addressing modes. The lowest 32 Bytes are grouped into 4

banks of 8 registers (R0 to R7). 2 bits RS0 and RS1 in PSW register (see

Table 64)

select which bank is in use according to Table 63. This allows more efficient use of code

space, since register instructions are shorter than instructions that use direct address-

ing, and can be used for context switching in interrupt service routines.

8K Bytes

Secured Boot ROM

11FFFh

10000h

0000h

64K Bytes RAM

FFFFh

CODE

DATA

XDATA

Memory Controller

DFC

Bus

CPU

Bus

1 2 ... 44 45 46 47 48 49 50 51 52 53 54 ... 262 263

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