Atmel AT85DVK-07 Especificaciones descargar pdf (Pagina 116)

116

AT85C51SND3Bx

7632A–MP3–03/06

Reset Value = 0000 0000b

3 EORSTI

End Of Reset Interrupt Flag

Set by hardware when an “End Of Reset” has been detected by the USB

controller. This triggers an USB interrupt if EORSTE is set.

Shall be cleared by software. Setting by software has no effect.

2 SOFI

Start Of Frame Interrupt Flag

Set by hardware when an USB “Start Of Frame” PID (SOF) has been detected

(every 1 ms). This triggers an USB interrupt if SOFE is set.

1 MSOFI

Micro-Start Of Frame Interrupt Flag

Set by hardware when an USB “Micro-Start Of Frame” PID (µSOF) has been

detected (every 125 µs). This triggers an USB interrupt if MSOFE is set.

0 SUSPI

Suspend Interrupt Flag

Set by hardware when an USB “Suspend” ‘idle bus for 3 frame periods: a J state

for 3 ms) is detected. This triggers an USB interrupt if SUSPE is set.

Shall be cleared by software. Setting by software has no effect.

See Section “Suspend, Wake-Up and Resume” for more details.

Table 114. UDIEN Register

UDIEN (1.DAh) – USB Device Global Interrupt Enable Register

7 6 5 4 3 2 1 0

- UPRSME EORSME WAKEUPE EORSTE SOFE MSOFE SUSPE

Bit

Number

Bit

Mnemonic

Description

7 -

Reserved

The value read from these bits is always 0. Do not set these bits.

6 UPRSME

Upstream Resume Interrupt Enable Bit

Set to enable the UPRSMI interrupt.

Clear to disable the UPRSMI interrupt.

5 EORSME

End Of Resume Interrupt Enable Bit

Set to enable the EORSMI interrupt.

Clear to disable the EORSMI interrupt.

4 WAKEUPE

Wake-Up CPU Interrupt Enable Bit

Set to enable the WAKEUPI interrupt.

Clear to disable the WAKEUPI interrupt.

3 EORSTE

End Of Reset Interrupt Enable Bit

Set to enable the EORSTI interrupt. This bit is set after a reset.

Clear to disable the EORSTI interrupt.

2 SOFE

Start Of Frame Interrupt Enable Bit

Set to enable the SOFI interrupt.

Clear to disable the SOFI interrupt.

1 MSOFE

Micro-Start Of Frame Interrupt Enable Bit

Set to enable the MSOFI interrupt.

Clear to disable the MSOFI interrupt.

Bit

Number

Bit

Mnemonic Description

1 2 ... 111 112 113 114 115 116 117 118 119 120 121 ... 262 263

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