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AT85C51SND3Bx

7632A–MP3–03/06

PSI Addressing The AT85C51SND3Bx are accessible by a host in read or write at two different address

locations by setting or clearing the SA0 address signal. The data management is

detailed in following sections and differs depending on SA0 level.

Table 234 shows the

addressing truth table. Figure 100 and Figure 101 show the read and write host cycles.

Table 230. PSI Addressing Truth Table

Figure 100. Host Read Waveforms

Figure 101. Host Write Waveforms

Write Data Sampling In order to be compliant with hosts depending on write cycle timing, a delay from SRW

signal assertion can be programmed for sampling data written by the host. This delay is

programmable from 0 to 7 peripheral clock periods using PSWS2:0 bits in PSICON.

Fig-

ure 102 shows the write sampling delay waveform.

Depending on the system clock frequency, host may need to add wait states inside read

or write cycles.

SA0 SRD / SWR Selection

1 Read

Host reads the PSISTH register to get PSI status from both hardware and

software.

1 Write Host writes in the FIFO.

0 Read

DFC transfer (PSI is destination)

Host reads data from the source peripheral through the FIFO.

CPU transfer

Host reads data from the FIFO.

0 Write

DFC transfer (PSI is source)

Host writes data to the destination peripheral through the FIFO.

CPU transfer

Host writes data in the FIFO.

Read Data

SA0

SD7:0

SRD

Read PSISTH

SCS

SA0

SD7:0

SWR

Data Write

SCS

Data Write

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