
115
AT85C51SND3Bx
7632A–MP3–03/06
Registers
USB Device General Registers
Reset Value = 0000 0001b
Table 112. UDCON Register
UDCON (1.D9h) – USB Device General Control Register
7 6 5 4 3 2 1 0
- - - - - - RMWKUP DETACH
Bit
Number
Bit
Mnemonic
Description
7-2 -
Reserved
The value read from these bits is always 0. Do not set these bits.
1 RMWKUP
Remote Wake-up Bit
Set to send an “upstream-resume” to the host for a remote wake-up.
Cleared by hardware. Clearing by software has no effect.
See Section “Remote Wake-Up” for more details.
0 DETACH
Detach Bit
Set to physically detach de device.
Clear to reconnect the device. See Section “Detach” for more details.
Table 113. UDINT Register
UDINT (1.D8h) – USB Device Global Interrupt Register
7 6 5 4 3 2 1 0
- UPRSMI EORSMI WAKEUPI EORSTI SOFI MSOFI SUSPI
Bit
Number
Bit
Mnemonic
Description
7 -
Reserved
The value read from these bits is always 0. Do not set these bits.
6 UPRSMI
Upstream Resume Interrupt Flag
Set by hardware when the USB controller is sending a resume signal called
“Upstream Resume”. This triggers an USB interrupt if UPRSME is set.
Shall be cleared by software (USB clocks must be enabled before). Setting by
software has no effect.
5 EORSMI
End Of Resume Interrupt Flag
Set by hardware when the USB controller detects a good “End Of Resume”
signal initiated by the host. This triggers an USB interrupt if EORSME is set.
Shall be cleared by software. Setting by software has no effect.
4 WAKEUPI
Wake-up CPU Interrupt Flag
Set by hardware when the USB controller is re-activated by a filtered non-idle
signal from the lines (not by an upstream resume). This triggers an interrupt if
WAKEUPE is set.
Shall be cleared by software (USB clock inputs must be enabled before). Setting
by software has no effect.
See Section “Suspend, Wake-Up and Resume” for more details.
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