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AT85C51SND3Bx

7632A–MP3–03/06

OverRun Condition This error means that the speed is not adapted for the running application.

An OverRun condition occurs when a byte has been received whereas the previous one

has not been read by the application yet.

The last byte (which generate the overrun error) does not overwrite the unread data so

that it can still be read. Therefore, an overrun error always indicates the loss of data.

Interrupt The SPI handles 3 interrupt sources that are the “end of transfer”, the “mode fault” and

the “transmit register empty” flags.

As shown in Figure 125, these flags are combined together to appear as a single inter-

rupt source for the C51 core.

The SPIF flag is set at the end of an 8-bit shift in and out and is cleared by reading

SPSCR and then reading from or writing to SPDAT.

The MODF flag is set in case of mode fault error and is cleared by reading SPSCR and

then writing to SPCON.

The SPTE flag is set when the transmit register is empty and ready to receive new data.

When SPTE interrupt source is enabled, SPIF flag does not generate any interrupt.

The SPI interrupt is enabled by setting ESPI bit in IEN1 register. This assumes inter-

rupts are globally enabled by setting EA bit in IEN0 register.

Figure 125. SPI Interrupt System

Registers

ESPI

IEN1.3

SPTEIE

SPSCR.1

SPI Controller

Interrupt Request

SPIF

SPSCR.7

MODF

SPSCR.4

SPTE

SPSCR.3

MODFIE

SPSCR.0

Table 251. SPCON Register

SPCON (1:91h) – SPI Control Register

7 6 5 4 3 2 1 0

SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0

Bit

Number

Bit

Mnemonic

Description

7 SPR2

SPI Rate Bit 2

Refer to Ta bl e 250 for bit rate description.

6 SPEN

SPI Enable Bit

Set to enable the SPI interface.

Clear to disable the SPI interface.

5 SSDIS

Slave Select Input Disable Bit

Set to disable SS in both master and slave modes. In slave mode this bit has no

effect if CPHA = 0.

Clear to enable SS in both master and slave modes.

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