Atmel AT85DVK-07 Especificaciones descargar pdf (Pagina 33)

AT85C51SND3Bx

7632A–MP3–03/06

Registers

Reset Value = 0000 0000b

Table 31. CKCON Register

CKCON (0.8Fh) – Clock Control Register

7 6 5 4 3 2 1 0

- WDX2 OSCAMP OSCF1 OSCF0 T1X2 T0X2 X2

Bit

Number

Bit

Mnemonic

Description

7 -

Reserved

The value read from this bit is always 0. Do not set this bit.

6 WDX2

Watchdog Clock Control Bit

Set to select the oscillator clock divided by 2 as watchdog clock input (X2

independent).

Clear to select the peripheral clock as watchdog clock input (X2 dependent).

5 OSCAMP

Oscillator Amplifier Control Bit

Set to optimize power consumption by disabling the oscillator amplifier when an

external clock is used.

Clear to enable the oscillator amplifier in case of crystal usage (default).

4-3 OSCF1:0

Oscillator Frequency Range Bits

Set this bits according to Table 23 to optimize power consumption.

2 T1X2

Timer 1 Clock Control Bit

Set to select the oscillator clock divided by 2 as timer 1 clock input (X2

independent).

Clear to select the peripheral clock as timer 1 clock input (X2 dependent).

1 T0X2

Timer 0 Clock Control Bit

Set to select the oscillator clock divided by 2 as timer 0 clock input (X2

independent).

Clear to select the peripheral clock as timer 0 clock input (X2 dependent).

0 X2

System Clock Control Bit

Clear to select 12 clock periods per machine cycle (STD mode, F

CPU

= F

PER

OSC

/2).

Set to select 6 clock periods per machine cycle (X2 mode, F

CPU

= F

PER

= F

OSC

1 2 ... 28 29 30 31 32 33 34 35 36 37 38 ... 262 263

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