Atmel AT85DVK-07 Especificaciones descargar pdf (Pagina 51)

AT85C51SND3Bx

7632A–MP3–03/06

The Figure 27 shows the memory segments configuration after bootstrap execution

along with an example of user memory segments configuration done during firmware

start-up. In this figure italicized address are the logical address within segments.

Figure 27. Memory Segment Configuration

Registers

Reset Value = 0000 0000b

0000h

FFFFh

FF00h

FEFFh

F000h

EFFFh

00h

FFh

256-byte DATA

000h

EFFh

3840-byte XDATA

60-Kbyte CODE

EFFFh

0000h

FFFFh

FF00h

FEFFh

E000h

DFFFh

00h

FFh

256-byte DATA

000h

1EFFh

7936-byte XDATA

56-Kbyte CODE

DFFFh

0000h

Default Configuration User Configuration Example

MEMCBAX = 00h

MEMXBAX = 78h

MEMDBAX = 7Fh

MEMCSX = EFh

MEMXSX = 0Eh

MEMCBAX = 00h

MEMXBAX = 70h

MEMDBAX = 7Fh

MEMCSX = DFh

MEMXSX = 1Eh

Table 64. PSW Register

PSW (S:8Eh) – Program Status Word Register

7 6 5 4 3 2 1 0

CY AC F0 RS1 RS0 OV F1 P

Bit

Number

Bit

Mnemonic

Description

7 CY

Carry Flag

Carry out from bit 1 of ALU operands.

6 AC

Auxiliary Carry Flag

Carry out from bit 1 of addition operands.

5 F0 User Definable Flag 0

4-3 RS1:0

Refer to Table 63 for bits description.

2 OV

Overflow Flag

Overflow set by arithmetic operations.

1 F1 User Definable Flag 1

0 P

Parity Bit

Set when ACC contains an odd number of 1’s.

Cleared when ACC contains an even number of 1’s.

1 2 ... 46 47 48 49 50 51 52 53 54 55 56 ... 262 263

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