Atmel AT85DVK-07 Especificaciones descargar pdf (Pagina 169)

169

AT85C51SND3Bx

7632A–MP3–03/06

Figure 79. Nand Flash Connection

Clock Unit The NFC clock is generated based on the clock generator as detailed in Section

"DFC/NFC Clock Generator", page 30. As soon as NFEN bit in NFCON is set, the NFC

controller receives its system clock and can then be configured.

Control Unit The Control unit configures the NFC and gives the user all the flexibility to interface the

NF devices. All the flash commands must be produced by the software, and the NFC

just sends to the Flash basic operations such as “read Id”, “write a byte”, “erase a

block”,

…

Configuration Descriptor Prior to any operation, the NFC must be configured with static information concerning

the NF devices connected to the product as well as other important information relevant

to the desired behavior. The configuration is done by writing a descriptor byte by byte in

the NFCFG register. The NF descriptor is composed of eight bytes (detailed in

Table 188). The first byte written is byte 0.

After writing a descriptor, a new one can be written to the NFC.

Table 188. Configuration Descriptor Content

IOVDD

NFRE

NFCE3:0

NFWE

NFALE

NFCLE

NFD7:0

NFWP

NF0

IOVSS

D7:0

ALE

CLE

VSS

VDD

NF1

D7:0

ALE

CLE

VSS

VDD

NF2

D7:0

ALE

CLE

VSS

VDD

NF3

D7:0

ALE

CLE

VSS

VDD

3012

SMC

Byte

Offset

Byte

Mnemonic

Description

0 NFPGCFG

NF Device Page Configuration Register

Refer to Table 189 for register content organization.

1 SMPGCFG

SMC Device Page Configuration Register

Refer to Table 189 for register content organization.

2 SCFG1

Sub Configuration Register 1

Refer to Table 190 for register content organization.

3 SCFG2

Sub Configuration Register 2

Refer to Ta b l e 191 for register content organization.

4 FPBH NF Device First Protected Block Address Registers

First address block of protected area. Refer to Section “Write Protection” for

detailed information.

Reset Value is 0000 0000b, 0000 0000b.

5 FPBL

6 LPBH NF Device Last Protected Block Address Registers

First address block of protected area. Refer to Section “Write Protection” for

detailed information.

Reset Value is 0000 0000b, 0000 0000b.

7 LPBL

1 2 ... 164 165 166 167 168 169 170 171 172 173 174 ... 262 263

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