
13
Atmel ATWILC1500-MR [PRELIMINARY DATASHEET]
Atmel-42376A-ATWINC1500-MR210P-SmartConnect-Datasheet_102014
5.4 Host Interface Power-up Sequence Timing Diagram
Figure 5-4. Host Interface Power up Sequence Timing Diagram
6. VDDIO Load Switch
The ATWINC1500-MR210P module is designed with a load switch in series with the VDDIO supply. The load
switch is controlled by the Chip_En pin of the module (Module pin 22). When Chip_En is high, the load switch is
turned on. When Chip_En is low the load switch is open and VDDIO is disconnected from the ATWINC1500-
MR210P. When the VDDIO supply to the ATWINC1500-MR210PA is disconnected it is important that none of
the pins to the ATWINC1500-MR210PA is in a high state. Figure 6-1 on page 14 shows the ESD structure of the
pins of the ATWINC1500 and Figure 6-2 on page 14 shows the current path through the ESD diode from a pin
that is being driven high to the VDDIO supply of the device. In effect, if VDDIO is disconnected from the external
power supply and a high level is driven on to a pad of the device, the device will be powered up through the pad.
Comentarios a estos manuales