
AT7910E [DATASHEET]
7796G AERO 02/13
5.2 Pin Description
Table 5-2. Pin Description
3.3V Power for the device
LVDS Power reference for the device
Bias for the PLL VCO (Rvco)
System Clock - Provides the reference clock for all the
AT7910E modules except the SpaceWire interface
receivers
Asynchronous active low system reset
PLL feedback divider configuration - Set the internal PLL
output clock rate
Differential output pair - Data part of Data-Strobe
SpaceWire link 1 to 8.
Differential output pair - Strobe part of Data-Strobe
SpaceWire link 1 to 8.
Differential input pair - Data part of Data-Strobe
SpaceWire link 1 to 8.
Differential input pair - Strobe part of Data-Strobe
SpaceWire link 1 to 8.
Output data from external port zero FIFO.
Bit eight determines the data type data, EOP or EEP
Input data from external port zero FIFO.
Bit eight determines the data type data, EOP or EEP
FIFO ready signal for external output port zero. When high
the FIFO has data. When low the FIFO is empty
Asserted Low to read from the external output port zero
FIFO.
FIFO ready signal for external input port zero. When high
there is space in the FIFO so it can be written to. When
low the FIFO is full.
Asserted Low to write to the external input port zero FIFO.
Output data from external port one FIFO.
Bit eight determines the data type data, EOP or EEP
Input data from external port one FIFO.
Bit eight determines the data type data, EOP or EEP
FIFO ready signal for external output port one. When high
the FIFO has data. When low the FIFO is empty
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