Atmel AVR AT90S8515-4 Manual de usuario

1Features• Utilizes the AVR® RISC Architecture• AVR – High-performance and Low-power RISC Architecture– 118 Powerful Instructions – Most Single Clock

10AT90S85150841GS–09/01Packaging Information44A1.20(0.047) MAX10.10(0.394) 9.90(0.386)SQ12.25(0.482)11.75(0.462)SQ0.75(0.030)0.45(0.018)0.15(0.006)0.

11AT90S85150841GS–09/0144J1.14(0.045) X 45˚PIN NO. 1IDENTIFY0.813(0.032)0.660(0.026)1.27(0.050) TYP12.70(0.500) REF SQ1.14(0.045) X 45˚0.51(0.020)MAX

12AT90S85150841GS–09/0140P652.71(2.075)51.94(2.045)PIN113.97(0.550)13.46(0.530)0.38(0.015)MIN0.56(0.022)0.38(0.015)REF15.88(0.625)15.24(0.600)1.65(0.0

© Atmel Corporation 2001.Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standa

2AT90S85150841GS–09/01Pin Configurations

3AT90S85150841GS–09/01Description The AT90S8515 is a low-power CMOS 8-bit microcontroller based on the AVR RISCarchitecture. By executing powerful ins

4AT90S85150841GS–09/01one clock cycle. The resulting architecture is more code efficient while achievingthroughputs up to ten times faster than conven

5AT90S85150841GS–09/01current if the pull-up resistors are activated. The Port D pins are tri-stated when a resetcondition becomes active, even if the

6AT90S85150841GS–09/01Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addres

7AT90S85150841GS–09/01Instruction Set SummaryMnemonic Operands Description Operation Flags # ClocksARITHMETIC AND LOGIC INSTRUCTIONSADD Rd, Rr Add Two

8AT90S85150841GS–09/01DATA TRANSFER INSTRUCTIONSMOV Rd, Rr Move between Registers Rd ← Rr None 1LDI Rd, K Load Immediate Rd ← KNone1LD Rd, X Load Indi

9AT90S85150841GS–09/01Note: Order AT90S8515A-XXX for devices with the FSTRT Fuse programmed.AT90S8515 Ordering InformationSpeed (MHz) Power Supply Ord